A DC-link Capacitor Voltage Balancing with CMV Elimination using only the Switching State Redundancies for a Reduced Switch Count Multi-Level Inverter fed IM Drive

Common mode voltage (CMV) variations in PWM inverter-fed drives generate unwanted shaft and bearing current resulting in early motor failure. Multilevel inverters reduce this problem to some extent, with higher number of levels. But the complexity of the power circuit increases with an increase in the number of inverter voltage levels. In this paper a five-level inverter structure is proposed for open-end winding induction motor (IM) drives, by cascading only two conventional two-level and three-level inverters, with the elimination of the common mode voltage over the entire modulation range. The DC link power supply requirement is also optimized by means of DC link capacitor voltage balancing, with PWM control., using only inverter switching state redundancies. The proposed power circuit gives a simple power bits structure.

A Multilevel inverter structure with cascaded two level and three level inverters for IM drive with CMV elimination and DC link capacitor voltage balancing

Common mode voltage (CMV) variations in PWM inverter-fed drives generate unwanted shaft and bearing current resulting in early motor failure. Multilevel inverters reduce this problem to some extent, with higher number of levels. But the complexity of the power circuit increases with an increase in the number of inverter voltage levels. In this paper a five-level inverter structure is proposed for open-end winding induction motor (IM) drives, by cascading only two conventional two-level and three-level inverters, with the elimination of the common mode voltage over the entire modulation range. The DC link power supply requirement is also optimized by means of DC link capacitor voltage balancing, with PWM control, using only inverter switching state redundancies. The proposed power circuit gives a simple power bus structure.

A Dual Seven-Level Inverter Supply for an Open-End Winding Induction Motor Drive

This paper develops a seven-level inverter structure for open-end winding induction motor drives. The inverter supply is realized by cascading four two-level and two three-level neutral-point-clamped inverters. The inverter control is designed in such a way that the common-mode voltage (CMV) is eliminated. DC-link capacitor voltage balancing is also achieved by using only the switching-state redundancies. The proposed power circuit structure is modular and therefore suitable for fault-tolerant applications. By appropriately isolating some of the inverters, the drive can be operated during fault conditions in a five-level or a three-level inverter mode, with preserved CMV elimination and DC-link capacitor voltage balancing, within a reduced modulation range.

Stability and structural transitions of tomato aspermy virus and cucumber mosaic virus

The properties of the S-strain of cucumber mosaic virus (S-CMV) and the B-strain of tomato aspermy virus (B-TAV) have been studied with respect to their (i) size and sedimentation behavior, (ii) requirement of divalent metal ions for stability, (iii) sensitivity towards chloride salts and the anionic detergent sodium dodecyl sulfate, (iv) solubility in ammonium sulfate-containing buffers, and (v) pH-dependent structural transitions. The results indicate that the coat protein of B-TAV is more hydrophobic than the other well-studied strains of TAV and CMV. Circular dichroism and uv absorption studies reveal pH-dependent structural transitions, although these do not result in particle swelling. These transitions appear to alter the strength of protein-nucleic acid interactions in these viruses.

High level stable expression of rat brain type IIA sodium channel ?-subunit in CHO cells

The neuronal sodium channels are responsible for the rising phase of action potential and are composed of three subunits, of which the alpha-subunit has been shown to be adequate for most of its functional properties. We have stably expressed the rat brain type IIA sodium channel alpha-subunit in CHO cell tine using a CMV promoter-based vector. The expression was confirmed by detecting a 6.5 kb RNA corresponding to sodium channel alpha-subunit using Northern hybridization. The cells stably expressing the alpha-subunit, yield isolated sodium currents of amplitudes greater than 4nA when studied in whole-cell configuration of the patch-clamp technique. The sodium currents are characterized by activation and inactivation properties similar to neuronal sodium channels, and are blocked by the voltage gated sodium channel blocker tetrodotoxin (TTX).

A five level inverter scheme with common mode volatge elimination by cascading conventional two level and three level NPC inverters for an induction motor drive

Common-mode voltage generated by the PWM inverter causes shaft voltage, bearing current and ground leakage current in induction motor drive system, resulting in an early motor failure. This paper presents a common-mode elimination scheme for a five-level inverter with reduced power circuit complexity. The proposed scheme is realised by cascading conventional two-level and conventional NPC three-level inverters in conjunction with an open-end winding three-phase induction motor drive and the common-mode voltage (CMV) elimination is achieved by using only switching states that result in zero CMV, for the entire modulation range.

A Hybrid Five-Level Inverter With Common-Mode Voltage Elimination Having Single Voltage Source for IM Drive Applications

A new hybrid five-level inverter topology with common-mode voltage (CMV) elimination for induction motor drive is proposed in this paper. This topology has only one dc source, and different voltage levels are generated by using this voltage source along with floating capacitors charged to asymmetrical voltage levels. The pulsewidth modulation (PWM) scheme employed in this topology balances the capacitor voltages at the required levels at any power factor and modulation index while eliminating the CMV. This inverter has good fault-tolerant capability as it can be operated in three-or two-level mode with CMV elimination, in case of any failure in the H-bridges. More voltage levels with CMV elimination can be realized from this topology but only in a limited range of modulation index and power factor. Extensive simulation is done to validate the PWM technique for CMV elimination and balancing of the capacitor voltages. The experimental verification of the proposed inverter-fed induction motor is carried out in the linear modulation and overmodulation regions. The steady-state and transient operations of the drive are verified. The dynamics of the capacitor voltage balancing is also tested. The experimental results demonstrate that the proposed topology can be considered for industrial drive applications.

Reduced common-mode voltage operation of a new seven-level hybrid multilevel inverter topology with a single DC voltage source

In this study, analysis of extending the linear modulation range of a zero common-mode voltage (CMV) operated n-level inverter by allowing reduced CMV switching is presented. A new hybrid seven-level inverter topology with a single DC supply is also presented in this study and inverter operation for zero and reduced CMV is analysed. Each phase of the inverter is realised by cascading two three-level flying capacitor inverters with a half-bridge module in between. Proposed inverter topology is operated with zero CMV for modulation index <86% and is operated with a CMV magnitude of V-dc/18 to extend the modulation range up to 96%. Experimental results are presented for zero CMV operation and for reduced common voltage operation to extend the linear modulation range. A capacitor voltage balancing algorithm is designed utilising the pole voltage redundancies of the inverter, which works for every sampling instant to correct the capacitor voltage irrespective of load power factor and modulation index. The capacitor voltage balancing algorithm is tested for different modulation indices and for various transient conditions, to validate the proposed topology.